The present invention relates generally to operating a processor-based system outside of an operating system and, more particularly, to operations occurring in a system management mode of the system.
In modern computer systems, system management activities such as those associated with temperature, voltage, and front panel button monitoring may be performed by routines that operate transparently to the operating system. One example of such a mode is termed System Management Mode (SMM) and may be entered through activation of an external system interrupt pin which generates a System Management Interrupt (SMI). In response to an SMI, the SMM may handle the event with system management functions such as reduced power consumption, debugging, or hardware emulation.
System management functions may be performed independently of the operating system. Before handling a system management event, the processor's internal state may be saved to a separate, protected and dedicated memory space, referred to as SMM random access memory (SMRAM). Then, firmware may control product-specific hardware features.
Chipsets such as memory controller hubs (MCHs) and I/O Controller Hubs (ICHs) compatible with a so-called Intel Architecture (IA), such as an IA-32 processor available from Intel Corporation (Santa Clara, Calif.) support SMM and SMI. SMM provides an essential context for BIOS to implement system features and chipset workarounds. SMM also serves as the security context for features such as protected flash access.
Recent chipsets provide the capability to alias SMM memory to high address space (HSEG) above 1 megabytes (MB), and/or reserve additional SMM memory from the top of system memory (TSEG). While this capability allows basic input/output system (BIOS) to cache SMM memory for improved SMI performance, when write-back (WB) cache is used for SMM address space, the processor does not explicitly preserve its SMM context when that data is written to cache. Instead, the SMM context is sampled when cached data is written back to system memory. Thus memory writes that occur within SMM may appear to be outside SMM when the cache line is evicted. This presents a significant challenge for the MCH to determine whether the cached data should be written to SMM memory. While the MCH allows cache-line writes to SMM memory regardless of processor context or SMM memory configuration, several drawbacks exist including requiring extra logic in the MCH to handle cache-line writes differently than other SMM memory writes and reduced system reliability and security. Thus, a need exists to improve consistency and security of SMM memory.